The present invention relates to an image sensing pixel cell architecture, and particularly to an image sensing pixel cell architecture that provides high sensitivity, relatively lag-free response and an electronic shutter.
Recently, CMOS image sensors characterized by their low power consumption have been in great demand as an image capturing device for machine vision applications. Typically, an image sensor includes at least several hundred pixel cells arranged in a grid. Also, in many machine vision applications each pixel cell is optimized for sensing particular types of light, e.g., infra-red.
To capture a still image of a fast moving object, a CMOS image sensor typically operates an electronic shutter for each pixel cell. However, to freeze an image of a fast moving object, the electronic shutter can only be held open for a relatively brief period of time. As a result, only a small amount of light is incident upon the pixel cell for integration. Since the amount of incident light is relatively small, it is difficult for an image sensor to output a signal that represents an accurate image of a fast moving object. To accommodate for this difficulty, pixel cells are often provided with a relatively high sensitivity. Unfortunately, in the past, these pixel cells with high sensitivity had significant lag that caused blur in an image of a fast moving object Therefore, there has been a need for a highly sensitive and lag free pixel cell architecture with an electronic shutter for use in CMOS image sensors.
The present invention is directed to a photogate based pixel cell architecture that provides relatively low lag, high sensitivity for infrared light and high voltage swing (dynamic range) with an electronic shutter. This invention eliminates the need for a transfer gate; and prevents overexposure during idle and storage cycles. Blooming cannot occur during these cycles because the photogate is continuously reset. The invention further improves the dynamic range of each pixel cell by enabling the implementation of the reset gate and the electronic shutter with PMOS devices.
In one embodiment of the invention, a photogate is disposed over a Pxe2x88x92 substrate. Electrons collect in a region underneath the photogate when a potential on the photogate is high and light is incident on the photogate. An N+ floating diffusion area is disposed adjacent to the photogate and on the surface of the Pxe2x88x92 substrate. A first and a second capacitance are disposed on opposite sides of a shutter transistor. The N+ floating diffusion area and the first and second capacitances store electrons that migrate from underneath the photogate when the potential on the photogate is low. A reset transistor is coupled between the N+ floating diffusion area and a supply voltage. The electrons stored in the N+ floating diffusion area move to the supply voltage when the reset transistor conducts. Also, the gate of a first transistor is coupled to the shutter transistor. When the shutter transistor is non-conducting, a signal voltage representing light incident on the photogate is stored on the second capacitance that is disposed on one side of the shutter transistor and coupled to the gate of the first transistor, so that the signal voltage is presented at the gate of the first transistor for read out.
In yet another embodiment of the invention, when the shutter transistor is conducting, the electrons stored in the second capacitance are converted into the signal voltage. Also, the first capacitance and second capacitance include parasitic capacitances, source capacitance of the reset transistor, channel capacitance of the shutter transistor and the junction capacitance of the N+ floating diffusion area.
In still another embodiment of the invention, the reset transistor and the shutter transistor are PMOS devices that enable a larger voltage swing inside the pixel cell and greater dynamic range for the signal voltage.
In a further embodiment of the invention, the reset transistor and the shutter transistor are NMOS devices that enable a small size for the pixel cell.
In another embodiment of the invention, a Pxe2x88x92 well is disposed around the circumference of the photogate. The Pxe2x88x92 well provides lateral confinement for electrons collected underneath the photogate. Also, the absence of the Pxe2x88x92 well beneath the photogate enables electrons induced by infrared light to collect underneath the photogate.
In yet another embodiment, at least a correlated double sampling method is employed to read out the voltage signal. Also, the source follower circuit includes the first transistor and a second transistor. When the second transistor conducts, the signal is available for read out.
In still another embodiment, an image sensor includes a plurality of pixel cells arranged in a grid.
These and other features as well as advantages, which characterize the invention, will be apparent from a reading of the following detailed description and a review of the associated drawings.